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Color TFT LCD Driver
MN838896
1. Type
CMOS LSI source driver for color TFT LCD panels
2. Overview
This LSI converts the digital display data from a personal computer, portable device, or other source into analog signals for driving a color TFT LCD panel.
3. Features
(1) Power saving driver (2) Built in DA converter accepting 6-bit digital input (for 262,144 colors) (3) Choice of 408, 396, 372, and 360 drive outputs (4) Input data bus at pixel level (5) Choice of output data format: gray scale or binary (6) Thirteen reference voltage inputs for producing 10 segment gamma adjustment graph. (7) Set output voltage inflection points at data values 00, 01, 07, 0F, 17, 1F, 27, 2F, 37, 3E, and 3F. (8) Prechargeless drive circuits (9) Support for serial cascade connections (10) Automatic internal clock stop after fixed number of data inputs (11) Choice of shift register shift direction: right or left (12) Gray scale data inversion available every clock cycle (13) Low voltage operation: 1.8 V (typ.) for logic circuits; 3.5 V (typ.) for analog circuits (14) Maximum operating clock frequency: 10 MHz (15) Power save function for cutting off current to outputs, fixing them at high impedance (16) Switching of gamma adjustment resistors for binary output, high impedance output, etc.
Publication date: August 2002
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4. Internal Block Diagram
YY1 YX1 YZ1 YX136 YZ136 YY136
BVDD
AVDD2 AVSS2 AVDD1 AVSS1
Output circuits
AVDD AVSS VREFR VREF 0 to 10 VREFL PS 6 MODE3 LD 6 6 6 6 6 408/396/ 372/360
RSW 11
DA converter
Two line latches, 408/396/372/360 x 6 bits
INV DX0 to 5 DY0 to 5 DZ0 to 5
6 6 6
Latch
6
6
6
6
6
6
1 STHR STHL
136
Shift register, 136/132/124/120 bits
FY TEST1 TEST2
MODE1 MODE2 RL
DV SS
DVDD
Figure 4.1 Block Diagram
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5. ) Descriptions Pin
Pin Name
I/O Direction
Pin Function
Description
DX0 to 5, DY0 to 5, DZ0 to 5
Input
The MODE3 input level specifies the format: Low level for gray scale (RGB); High level for binary. For gray scale input, DX5, DY5, and DZ5 represent the MSB; DX0, DY0, and DZ0, the LSB. Digital data input pins, Binary input uses only DX5, DY5, and DZ5. Always drive the unused pins gray scale (DX4 to DX0, DY4 to DY0, and DZ4 to DZ0) or binary format at either High or Low level, however. *DX5, DY5, DZ5* The data logic when the INV input is at Low level is AVDD for Low level and AVSS for High level. Driving INV at High level reverses the data logic.
YX1 to 136, YY1 to 136, YZ1 to 136
Output
Analog image output pins
These signals drive the LCD panel.
These I/O pins are for the internal shift register's start pulses. The following table indicates data shift direction by start pulses during face up.
STH R, STHL
I/O
Start pulse I/O pins
RL = H STHR STHL
Right shift input Right shift output
RL = L
Left shift output
Left shift input
RL
Input
Shift direction input pin Shift clock input pin Data load input pin Data inversion control input pin
This specifies the shift direction: High level for right; Low level for left. H: Right shift input (YX,YY,YZ1 136) L: Left shift input (YX,YY,YZ136 1) This accepts the transfer clock for the shift register High level input enables transfer, synchronized with rising edges in the FY signal, of the LCD drive data from the builtin DA converter.
FY LD
Input Input
INV
Input
High level input reverses the logic for data input. This signal can be switched anywhere except the latch signal, rising edges in the FY signal.
These specify the number of LCD panel drive outputs.
MODE1, 2
Input
Number of drive outputs select pin
MODE1 MODE2
Number of drive outputs
Unused pins None
High High Low Low
High Low
408 396
YX67 to YX70 YY67 to YY70 YZ67 to YZ70 YX63 to YX74 YY63 to YY74 High 372 YZ63 to YZ74 YX61 to YX76 YY61 to YY76 Low 360 YZ61 to YZ76 *Unused pins have high-impedance output
MODE3
Input
Input format select pin
This specifies the data input format: gray scale or binary. High level: Binary. DX5, DY5, and DZ5 only. )))))))The DA converter is off. Low level: Gray scale. DX5 to DX0, DY5 to DY0, and DZ5 to DZ0. The DA converter is on.
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Pin Name RSW
I/O Direction
Pin Function Gamma adjustment resistor select control
Description This controls the use of gamma adjustment resistors. Note that switching need not be synchronized with the FY signal. Low level: Enable (gray scale output) High level: Disable (binary output, , high-impedance output, etc.) Enable the use of these resistors at least five H clock cycles before switching to gray scale output. High level input at a rising edge in the FY signal cuts off current to outputs, fixing them at high-impedance. High level: High-impedance outputs. No current to )))))))operational amplifier or other components. Low level: Normal operation Normally fix these inputs both at Low level. Low level: Normal operation High level: Test mode
Input
PS
Input
Power save function select pin
TEST1 TEST2
Input
TEST input pins
TEST1 TEST2 Operating Mode Low Normal operation Low
Switch gamma adjustment resistors
Low High
VREF0 to 10, R, L AVDD AVSS AVDD1 AVSS1 Input Input Input Input Input Gamma adjustment potential input pin Analog power supply Analog ground Analog power supply
High OFF when the PS pin input is
at High level
X
Boost image output drive power
This input is the gamma adjustment potential input pin for the DA converter. This is the power supply for the DA converter's analog circuits. This is the power supply for the output analog circuits.
Analog ground This is the ground for the output analog circuits and the binary Ground for analog circuits drive circuits. and binary drive signals Analog power supply Analog ground
This is the power supply for the circuits protecting the output circuits.
AVDD2 AVSS2 BV DD DVDD DVSS COM1 to 4 DUMMY
Input Input Input Input Input
Binary drive power supply This is the power supply for the binary drive output signals. Digital power supply
This is the power supply for the digital circuits.
Digital ground Through connections Dummy pins
These provide straight connections to the corresponding output pins. They are not connected to other circuits. These are dummies. They are not connected to other circuits.
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6. Description of Operation
6.1 Functional Description
The MODE3 pin offers a choice of 6-bit gray scale data or 1-bit binary data. The MODE1 and MODE2 pins specify the number of outputs. The following Table summarizes the effects of MODE3 and RL input levels on I/O pins when both MODE1 and MODE2 are at High level (408 outputs).
)Table 6.1 MODE3 and RL Settings (MODE1 = MODE2 = High Level)
MODE3 RL Input pins
FX : 1 2 3
Data transfer direction
- 68 69 - - 134 - 135 - 136 YX1 - YX2 - YX3 - - YX68 - YX69 - - YX134 - YX135 - YX136 YY1 - YY2 - YY3 - - YY68 - YY69 - - YY134 - YY135 - YY136 YZ1 - YZ2 - YZ3 - - YZ68 - YZ69 - - YZ134 - YZ135 - YZ136 - YX2 - YX1
Data Output format
DX0 - 5 Low level (gray scale input) H DY0 - 5 DZ0 - 5 DX0 - 5 L DY0 - 5 DZ0 - 5 DX5 H High level (binary input) DY5 DZ5 DX5 L DY5 DZ5
YX136 - YX135 - YX134 - - YX69 - YX68 - - YX3 YY136 - YY135 - YY134 - - YY69 - YY68 - - YY3 YZ136 - YZ135 - YX134 - - YZ69 - YZ68 - - YZ3 YX1 - YX2 - YX3 YY1 - YY2 - YY3 YZ1 - YZ2 - YZ3
64-level analog outputs
- YY2 - YY1 - YZ2 - YZ1
- - YX68 - YX69 - - YX134 - YX135 - YX136 - - YY68 - YY69 - - YY134 - YY135 - YY136 - - YZ68 - YZ69 - - YZ134 - YZ135 - YZ136 - YX2 - YX1 - YY2 - YY1 - YZ2 - YZ1 Binary digital outputs
YX136 - YX135 - YX134 - - YX69 - YX68 - - YX3 YY136 - YY135 - YY134 - - YY69 - YY68 - - YY3 YZ136 - YZ135 - YX134 - - YZ69 - YZ68 - - YZ3
The following unused pins have high-impedance output. 396 outputs: YX67 - YX70, YY67 - YY70, and YZ67 - YZ70 372 outputs: YX63 - YX74, YY63 - YY74, and YZ63 - YZ74 360 outputs: YX61 - YX76, YY61 - YY76, and YZ61 - YZ76
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MN838896 6.2 Relationships Between Data Input and Output Pins
(1) Gray scale data input (MODE3 = Low) The following summarizes the relationships between data input and output pins for gray scale data input (MODE3 = Low). So, binary data input is naturally ignored during gray scale data input. MODE3 = Low, RL = High Rn Bn Gn
n=1, 2, ,136 6 6 6 DX0 to 5 DY0 to 5 Source driver shifts right (RL = High) DZ0 to 5 YX1 YY1 YZ1 YX2 YY2 YZ2 408 outputs
YX136YY136 YZ136
R1 R1
B1 B1
G1 G1
R2 R2
B2 B2
G2 G2
R136 B136 G136 R136 B136 G136
R1
B1
G1
R2
B2
G2
R136 B136 G136
MODE3 = Low, RL = Low
R1 R1 B1 B1 G1 G1 R2 R2 B2 B2 G2 G2
408 outputs R136 B136 G136 R136 B136 G136
R1
B1
G1
R2
B2
G2
R136 B136 G136
Rn Bn Gn
n=1, 2, ,136
6 6 6
YZ136 YY136YX136YZ135YY135YX135 DZ0 to 5 DY0 to 5 DX0 to 5
YZ1 YY1 YX1
Source driver shifts left (RL = Low)
(2) Binary input (MODE3 = High) Binary input uses only the pins DX5, DY5, and DZ5. The relationships between data input and output pins are otherwise the same. So, binary data input is naturally ignored during gray scale data input.
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MN838896 6.3 Power Save Function
High level PS pin input at a rising edge in the FY signal cuts off current to outputs, fixing them at high-impedance. FY LD PS YX1 to 136, YY1 to 136, YZ1 to 136
Hi-Z
Figure 6.3 High-Impedance Output Interval
6.4 Blanking Interval The following timing chart summarizes the relationships between the load data (LD) and start pulse (STHR and STHL) inputs and the blanking interval.
FY Start pulse inputs STHR (RL = High) STHL (RL = Low) LD DX/DY/DZ0 to 5
N-4 N-3 N-2 N-1 N
2FY(Min)
At least two FY cycles
1FY
At least zero FY cycles
1
2
3
4
Final data input Blanking interval
First data input for first line
Figure 6.4 Blanking Interval 6.5 Data Inverse Function
Driving the INV input at High level inverts all bits in the data input.
FY DX 0 to 5 INV
Internal IDX0 data 00 00 00 07 3F 3F 3F 00 00 05 08
to 5
3F
00
3F
07
3F
00
3F
00
00
05
08
Driving the INV input at High level inverts all bits in the data input.
Figure 6.5 Data Inverse Function
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MN838896 6.6 Switching Input Formats
The following timing chart summarizes the relationships between changes in input format and the subsequent changes in output. FY Start pulse inputs STHR (RL = High) STHL (RL = Low) MODE3 LD
Valid input data
Binary data input
Gray scale data input
YX1 to 136, YY1 to 136, YZ1 to 136
Binary data output
Gray scale data output
Figure 6.6.1 Switching Formats (1/2)
The LSI drives the output pins at high-impedance for one FY cycle when changing output formats. FY LD
YX1 to 136, Binary data output YY1 to 136, (or gray scale YZ1 to 136 data output)
Hi-Z
Binary data output (or gray scale data output)
Output switching interval
Figure 6.6.2 Switching Formats (2/2)
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MN838896 6.7 Cascade Connection
(1) RL = High
Driver A starts latching data one FY cycle after receiving a start pulse (STHR). It asserts the carry signal (STHL) one FY cycle before latching the last data and then stopping. MODE1 = MODE2 = High (408 outputs): 135 FY cycles MODE1 = High, MODE2 = Low (396 outputs): 131 FY cycles MODE1 = Low, MODE2 = High (372 outputs): 123 FY cycles MODE1 = MODE2 = High (360 outputs): 119 FY cycles Cascade Connection Driver B starts latching data one FY cycle after receiving the carry signal (STHL) from driver A. Note: Although the carry signal (STHL) pulses are two FY cycles long, only the first cycle counts. The next driver treats the two cycles as a single pulse.
135 FY cycles (408 outputs) FY 1FY Pulse #1 1FY 1FY Pulse #2
1 2 3 135 136 137 138 139 140
DATA
LCD controller 6-bit RGB data or 1-bit data
Data latched by driver A
Data latched by driver B
(1)
Start pulse
STHR SRH L
(2)
STHR STHL STHR STHL
Driver A
Driver B Figure 6.7 Serial Cascade Connection
Driver C
(2) RL = Low
The start pulse input is from STHL; the carry output, from STHR. Apart from that, operation is the same as for RL = High.
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6.8 Relationship between Input Data and Output Voltage 6.8.1 Built-In Gamma Adjustment Resistors
The output voltage depends on the input data and thirteen gamma adjustment voltages (VREF x, x = H, 0 to 10, L). See graph and conversion table on the next two pages.
VREFR
Inside LSI
VREF0 R0
VREF1
VREF2
R1
VREF3
R2
The LSI contains ten divider resistances and two switches between VREG H and VREG L. Table 6.8 summarizes the formulas for calculating the output voltages from the voltages applied to pins VREF x, x = 0 to 10. Applying voltages only to VREG H and VREG L produces the default graph shown in Figure 6.8.2. Note that we recommend the use of an operational amplifier or similar means to guarantee low-impedance input to the VREG pins. The RSW pin input controls the two switches between VREG H and VREG L, allowing the user application system to conserve power by cutting the current flowing between the two pins. (Note 1) The adjustment voltages (VREF x, x = H, 0 to 10, L) must satisfy one of the following two relationships.
VREF4
R3
VREF5 VREF6
R4
or
AVDD > VREFR VREF0 VREF1 VREF10 VREFL > AVSS AVDD > VREFL VREF10 VREF9 VREF0 VREFR > AVSS
R5
Do not change these voltages while the chip is in operation.
VREF7
R6 R7
VREF8
The following are the values for the internal resistances R0 to R9. Gamma Adjustment Resistances R0 0.00 1.02 0.83 0.66 0.51 0.51 0.64 0.80 1.00 0.14
VREF9
R8
R1 R2 R3 R4 R5
VREF 10
R9
VREF L
R6 R7 R8 R9
Figure 6.8.1 Built-In Gamma Adjustment Resistors
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6.8.2 Relationship between Input Data and Output Voltage
The following Figure gives the gamma adjustment curve for INV = Low.
AVDD VREF 0 VREF 1
VREF 2
VREF 3
Output voltage
VREF 4
VREF 5
VREF 6
VREF 7
VREF 8
VREF 9 VREF 10 AVSS
00 01
07
0F
17
1F Input data
27
2F
37
3E3F
Figure 6.8.2 Relationship between Input Data and Output Voltage
(AVDD > VREFR VREF0 VREF1 ... ... VREF10 VREFL > AVSS )
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6.8.3 Relationship between Reference Voltages and Output Voltages The following Table gives the formulas for converting input data for INV = Low.
Table 6.8 Relationship between Reference Voltages and Output Voltages
(AVDD > VREFR VREF0 VREF1 ... ... VREF10 VREFL > AVSS ) Input data 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Formula for calculating output voltage VREF0 VREF2 + (VREF1 to VREF2) x 6/7 VREF2 + (VREF1 to VREF2) x 5/7 VREF2 + (VREF1 to VREF2) x 4/7 VREF2 + (VREF1 to VREF2) x 3/7 VREF2 + (VREF1 to VREF2) x 2/7 VREF2 + (VREF1 to VREF2) x 1/7 VREF2 VREF3 + (VREF2 to VREF3) x 7/8 VREF3 + (VREF2 to VREF3) x 6/8 VREF3 + (VREF2 to VREF3) x 5/8 VREF3 + (VREF2 to VREF3) x 4/8 VREF3 + (VREF2 to VREF3) x 3/8 VREF3 + (VREF2 to VREF3) x 2/8 VREF3 + (VREF2 to VREF3) x 1/8 VREF3 VREF4 + (VREF3 to VREF4) x 7/8 VREF4 + (VREF3 to VREF4) x 6/8 VREF4 + (VREF3 to VREF4) x 5/8 VREF4 + (VREF3 to VREF4) x 4/8 VREF4 + (VREF3 to VREF4) x 3/8 VREF4 + (VREF3 to VREF4) x 2/8 VREF4 + (VREF3 to VREF4) x 1/8 VREF4 VREF5 + (VREF4 to VREF5) x 7/8 VREF5 + (VREF4 to VREF5) x 6/8 VREF5 + (VREF4 to VREF5) x 5/8 VREF5 + (VREF4 to VREF5) x 4/8 VREF5 + (VREF4 to VREF5) x 3/8 VREF5 + (VREF4 to VREF5) x 2/8 VREF5 + (VREF4 to VREF5) x 1/8 VREF5 Input data 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Formula for calculating output voltage VREF6 + (VREF5 to VREF6) x 7/8 VREF6 + (VREF5 to VREF6) x 6/8 VREF6 + (VREF5 to VREF6) x 5/8 VREF6 + (VREF5 to VREF6) x 4/8 VREF6 + (VREF5 to VREF6) x 3/8 VREF6 + (VREF5 to VREF6) x 2/8 VREF6 + (VREF5 to VREF6) x 1/8 VREF6 VREF7 + (VREF6 to VREF7) x 7/8 VREF7 + (VREF6 to VREF7) x 6/8 VREF7 + (VREF6 to VREF7) x 5/8 VREF7 + (VREF6 to VREF7) x 4/8 VREF7 + (VREF6 to VREF7) x 3/8 VREF7 + (VREF6 to VREF7) x 2/8 VREF7 + (VREF6 to VREF7) x 1/8 VREF7 VREF8 + (VREF7 to VREF8) x 7/8 VREF8 + (VREF7 to VREF8) x 6/8 VREF8 + (VREF7 to VREF8) x 5/8 VREF8 + (VREF7 to VREF8) x 4/8 VREF8 + (VREF7 to VREF8) x 3/8 VREF8 + (VREF7 to VREF8) x 2/8 VREF8 + (VREF7 to VREF8) x 1/8 VREF8 VREF9 + (VREF8 to VREF9) x 6/7 VREF9 + (VREF8 to VREF9) x 5/7 VREF9 + (VREF8 to VREF9) x 4/7 VREF9 + (VREF8 to VREF9) x 3/7 VREF9 + (VREF8 to VREF9) x 2/7 VREF9 + (VREF8 to VREF9) x 1/7 VREF9 VREF10
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7. Product Standards
A. Absolute Maximum Ratings
Item A1 A2 A3 A4 A5 A6 A7 A8 A9
Digital power supply voltage
Analog power supply voltage Binary drive power supply voltage
AVSS = DVSS = 0V
Symbol DVDD AVDD BVDD VI1 VI2 VO1 VO2 Topr Ta T stg
Rating - 0.3 to 6.5 - 0.3 to 6.5 - 0.3 to AVDD - 0.3 to DVDD +0.3 - 0.3 to AVDD +0.3 - 0.3 to DVDD +0.3 - 0.3 to AVDD +0.3 - 30 to +85 - 20 to +75 - 40 to +125
Unit V V V V V V V C C C
Digital input voltage Analog input voltage Digital output voltage Analog output voltage
Operating storage temperature
Operating ambient temperature
A10 Storage temperature
Note: The above absolute maximum ratings represent limits for avoiding damage to the product. They do not guarantee operation. * The above standards apply only to our standard package for the product.
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B. Operating Conditions
Item Digital power supply voltage Analog power supply voltage Binary drive power supply voltage Gamma adjustment reference voltages Operating frequency Drive load capacity Digital signal input capacity Symbol Conditions DVDD AVDD BVDD VREF, L, 0 to 10 f FY CY C IN
1 MHz
Ta = - 20 C to +75 C AVSS = DVSS = 0V
Rating MIN 1.65 3.0 2.6 0.1 TYP 1.8 3.5 3.5 MAX 3.6 5.5 AVDD
AVDD - 0.1
Unit V V V V MHz pF pF
B1 B2 B3 B4 B5 B6 B7
10 50 7 15
Notes (1) Use only direct connections to power supply pins sharing the same symbol (AVDD, DVDD, and BVDD). (2) Use only direct connections to ground pins sharing the same symbol (AVSS and DVSS). (3) Apply voltages in the following order: DVDD pins, logic input pins, AVDD pins, BVDD pins, and VREF x. Remove them in the reverse order. (4) Make sure that the following relationship applies at all times.
* The above standards apply only to our standard package for the product.
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C. Electrical Characteristics 1 DC Characteristics
Item C1 C2 C3 C4 C5 C6 C7
Analog operation power supply current (1) Analog operation power supply current (2) DVDD = 1.8V, AVDD = BVDD = 3.5V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Symbol Conditions Notes 6 and 7
The above, without loads Notes 9
MIN
TYP 1.8 0.8
MAX 4.5
Unit
ISS1 ISS2 ISS3 ISS4 ISS5 ISS6 ISS7
mA mA
Analog standby power supply current Binary drive operation power supply voltage Binary drive standby power supply current Digital operation power supply voltage Digital standby power supply current
PS = High Notes 6 and 7 Clock signal off Notes 5 and 6 Clock signal off 0.1 1.1
5 3.0 5 1.0 5
A mA A mA A
(5) Typical conditions
FY frequency of 10 MHz, raster period of 50 s, data pattern alternating between 00 and 3F every raster period, fixed VREF x (6) Maximum conditions FY frequency of 10 MHz, raster period of 50 s, data pattern alternating between 00 and 3F every raster period, fixed VREF x ISS1 ISS2 ISS3
A A
ISS6 ISS7
ISS4 ISS5
A
AVDD BVDD DVDD AVSS DVSS
DUT
YX01 YY01 YZ01 YX02 YY02 AVSS YZ136
75 pF
DUT : Device Under Test 0V
(7) The loads on the analog output pins are as shown. Note that the numbers for those load circuits sometimes change. (8) The following is the formula for calculating the power consumption with the loads described in note 6 above. ISS1 x AVDD + I SS6 x DVDD (consumption by gamma adjustment resistors not included) (9) This value is for reference only. It is not guaranteed. The above standards apply only to our standard package for the product. * The above standards apply only to our standard package for the product.
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DVDD = 1.8V, AVDD = BVDD = 3.5V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Item Symbol Conditions MIN TYP MAX Unit
1) Input pins (RL, LD, DX0 to 5, DY0 to 5, DZ0 to 5, FY, INV, PS, MODE1 to 3, RSW) C6 C7 C8 High level input Low level input Input leak current VIH1 VIL1 I LI1
0.8 x DVDD DVDD 0.2 x DVDD
V V A
0 -2
2
2) I/O pins (STHR, STHL) C9 C10 C11 C12 C13 High level input Low level input High level output Low level output Input leak current VIH2 VIL2 VOH1 VOL1 I LI2
0.8 x DVDD DVDD 0.2 x DVDD
V V V
0
IO = - 1.0 mA DVDD - 0.5 IO = 1.0 mA
0.5 -2 2
V A
3) Pull down pins (TEST1, TEST2) C14 C15 C16 High level input Low level input Pull down resistances VIH3 VIL3 R PD
0.8 x DVDD DV DD 0.2 x DVDD
V V k
0 140 280
560
* The above standards apply only to our standard package for the product.
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DVDD = 1.8V, AVDD = BVDD = 3.5V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Item Symbol Conditions MIN TYP MAX Unit
(3) Gamma adjustment resistances C17 C18 Total resistance Switch resistance R R SW
Between VREF 0 and VREF 10 Between VREF R and VREF 0, Between VREF L and VREF 10
25 25
40 50
55 100
k
10) Conditions VREF R (VREF L) = 3.400 V, VREF 0 (VREF 10) = 3.395 V And VREF R (VREF L) = 0.100 V, VREF 0 (VREF 10) = 0.105 V VREFR R SW VREF0
R
VREF10
R SW VREFL
* The above standards apply only to our standard package for the product.
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DVDD = 1.8V, AVDD = BVDD = 3.5V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Item Symbol Conditions MIN TYP MAX Unit
(4) Analog output pins (YX1 to 136, YY1 to 136, YZ1 to 136) High level output current (gray scale output) V x = 3.4 V VOUT = 2.4V
Note 11
C19
I OH1
- 0.05
mA
C20
I OL1
V x = 0.1 V VOUT = 1.1 V
Note 11 2.7 V V x
0.05
mA 20 10 20 25 20 25
C21
Average output voltage deviation
VO
0.8 V < V x < 2.7V
mV
V x 0.8 V
C22
Output voltage range
VO V x = 3.5 V VOUT = 2.5V
Note 11
AVSS +0.1
AVDD - 0.1
V
C23
High level output current (binary output)
I OH2
- 0.1
mA
C24
Low level output current (binary output)
I OL2
V x = 0.0 V VOUT = 1.0 V
Note 11
0.1
mA
(5) Through connection pins (COM1 to 4) C25 Wiring resistance R COM 7
Note: For further details on through connection pin wiring resistance, refer to the reference data attached to the delivery specifications.
11) VX is the output voltage for the analog output pin;
V OUT, the voltage applied to the pin. * The above standards apply only to our standard package for the product.
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(2) AC Characteristics
Item C26 FY period C27 FY High level pulse width C28 FY Low level pulse width C29 Data/INV setup time C30 Data/INV hold time C31 Start pulse setup time C32 Start pulse hold time C33 Start pulse Low level pulse width C34 Carry output delay time C35 LD signal High level pulse width C36 LD signal Low level pulse width C37
LD signal-start pulse setup time
DVDD = 1.8V, AVDD = BVDD = 3.5V, AVSS = DVSS = 0 V, Ta = 25 C
Rating Symbol Conditions MIN 100 45 45 20 20 20 20 2
C L = 15 pF
TYP
MAX
Unit ns ns ns ns ns ns ns
FY period
tp t wcH t wcL t st1 t hd1 t st2 t hd2 t wsL t d1
wldH
Duty = 50 %
50 2 2 2 20 20
ns
FY period FY period FY period
t wldL t st3 tst4 t hd4 t st5 t hd5 t st6 t hd6 t ng1 t ng2 t d2 t d3 t d4 t st7
Note 12) Note 12)
C38 LD-FY setup time C39 LD-FY hold time C40 MODE3 setup time C41 MODE3 hold time C42 PS setup time C43 PS hold time C44 Data input invalid interval C45 Final data timing C46 LCD drive signal delay 1 C47 LCD drive signal delay 2 C48 LCD drive signal stop time C49 RSW setup time
ns ns ns ns ns ns 1 1
FY period FY period s s s s
20 20 20 20
C L = 15 pF
Note 13)
20 30 5 280
C L = 15 pF Note 13), Note 14) C L = 15 pF
12) The reference point is the first FY rising edge after the rising edge in the start signal (STHR or STHL). 13) This time is defined as that taken for the driver output voltage to reach, within 6-bit precision, the target voltage. 14) The target output voltage shall be the output voltage just before the power save function takes effect--that is, the latter shall be assumed to have reached the target. * The above standards apply only to our standard package for the product.
SDF00029AEM 19
MN838896
AC Characteristics Timing Chart 1
tp
FY
DX0 to 5 DY0 to 5 DZ0 to 5 INV1
t wcH
V IL VIH
t wcL
t st1
t hd1
t st2
Input STHR (RL = High), STHL (RL = Low) Output STHL (RL = High) STHR (RL = Low)
t hd2
t wsL
t d1
VOH
FY
Input STHR (RL = High), STHL (RL = Low) DX0 to 5 DY0 to 5 DZ0 to 5 INV1
t ng1
t st5
t hd5
MODE3
t st3
LD
t wldH
LD
t wldL
t st7
RSW Note In the absence of any indication to the contrary, the following levels are assumed. VIH = VOH = 0.8 x DVDD VIL = VOL = 0.2 x DVDD
SDF00029AEM
20
MN838896
AC Characteristics Timing Chart 2
FY
t hd4 t st4
LD
t d2
YX1 to 136, YY1 to 136, Change in output formats YZ1 to 136 Highimpedance output Target output voltages
t d2
YX1 to 136, Change in output YY1 to 136, formats YZ1 to 136 Target output voltages
FY
t ng2
LD
DX0 to 5 DY0 to 5 DZ0 to 5 INV1
t st1
VALID VALID VALID
t hd1
INVALID
VALID
FY
t st6
PS
t hd6 t d4 t d3
High-impedance output
YX1 to 136, YY1 to 136, YZ1 to 136
Note In the absence of any indication to the contrary, the following levels are assumed. VIH = VOH = 0.8 x DVDD VIL = VOL = 0.2 x DVDD
SDF00029AEM
21
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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